1. Field of the Invention
The present invention relates to a method for correcting a layout pattern, and more particularly, to a method including a bevel correction for correcting a layout pattern.
2. Description of the Prior Art
In semiconductor manufacturing processes, in order to transfer an integrated circuit onto a semiconductor wafer, the integrated circuits from a database are first designed as a layout pattern and a photomask is then manufactured according to the layout pattern. Patterns on the photomask may then be able to be transferred to the semiconductor wafer. The steps mentioned above may be regarded as a photolithographic process. The layout pattern has to be extremely accurate for forming delicate integrated circuits so as to align with the patterns of the previous and following steps.
In the photolithographic process, deviations often occur when the patterns on the photomask are transferred onto the wafer surface and jeopardize the performance of the semiconductor device. Such deviations are usually related with the characters of the patterns to be transferred, the topology of the wafer, the source of the light and various process parameters.
There are many kinds of verification methods, correction methods and compensation methods for the deviations caused by the optical proximity effect, process rules (PRC) and lithography rules (LRC) to improve the image quality after transfer. Some of the known methods are called optical proximity correction (OPC), process rule check (PRC) and lithography rule check (LRC). The commercially available OPC software may test problems such as pitch, bridge, and critical dimension uniformity in the layout patterns. Such software may correct the standard layout patterns on the masks using the theoretical image, so as to obtain correctly exposed image patterns on the wafers.